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Abstract of SiCOI Wafers
SICOI (Silicon Carbide on Insulator) wafers represent an advanced composite substrate technology fabricated through either Smart Cut™ or Bonding & Thinning processes. ZMSH supply 4-6 inch 4H-SICOI wafers by integrating high-quality SiC thin films with insulating layers (SiO₂/AlN) on silicon or SiC substrates via hydrophilic bonding or plasma-activated bonding techniques. Smart Cut™ Process: Utilizes hydrogen ion implantation, low-temperature bonding, and precision exfoliation to achieve ultra-thin SiC layers (50nm-20μm) with thickness uniformity of ±20nm, ideal for high-frequency, low-loss devices. Grinding+CMP Process: Suitable for thicker film requirements (200nm to custom thicknesses) with ±100nm uniformity, offering cost efficiency for power electronics applications. ZMSH provide customizable conductive or semi-insulating SiC films, with options for ion implantation annealing optimization or direct thinning/polishing to meet diverse performance and cost requirements.
| Component | Property | Specification | Measurement Standard |
| 4H-SiC Film | Crystal Structure | Single-crystal 4H-SiC | ASTM F2094 |
| Defect Density | <10³ cm⁻² (threading dislocations) | ||
| Surface Roughness (Ra) | <0.5 nm | AFM measurement | |
| Semi-insulating Resistivity | >10⁶ Ω·cm | SEMI MF397 | |
| N-type Doping Range | 10¹⁶-10¹⁹ cm⁻³ | ||
| Thermal Conductivity | >300 W/(m·K) | ||
| SiO₂ Layer | Formation Method | Thermal oxidation | |
| Dielectric Constant (ε) | 3.9 | JESD22-A109 | |
| Breakdown Field Strength | >10 MV/cm | ||
| Interface Trap Density | <10¹¹ cm⁻²eV⁻¹ | ||
| Si Substrate | Thermal Expansion (CTE) | ~3.5×10⁻⁶/°C | |
| Wafer Bow (8-inch) | <50 μm | SEMI M1 | |
| Temperature Stability | >300°C | ||
| Integrated Performance | Wafer Size Support | 4-8 inch formats |
1. Power Electronics
EV Inverters: SiC MOSFETs on SICOI substrates operate at 1200V with 30% lower switching losses, compatible with 800V fast-charging systems.
Industrial Motor Drives: SICOI wafers with AlN insulating layers enhance heat dissipation by 50%, supporting >10kW module packaging.
2. RF & 5G Communications
mmWave Power Amplifiers: GaN HEMTs on semi-insulating SICOI achieve 8W/mm output at 28GHz with >65% efficiency.
Phased Array Antennas: Low dielectric loss (tanδ<0.001) minimizes signal attenuation for satellite communications.
3. Quantum Computing & Sensing
Spin Qubit Carriers: Ultrathin SiC films (<100nm) provide low-noise environments, extending coherence times beyond 1ms.
High-Temp MEMS Sensors: Stable operation at 300°C for aerospace engine monitoring.
4. Consumer Electronics
Fast-Charging ICs: SICOI-based GaN devices enable >200W charging with 40% smaller footprint.
As a leading wide-bandgap semiconductor substrate provider, we offer end-to-end technical support from R&D to mass production:
· Custom Development: Optimize SiC film thickness (nanoscale to microns), doping (N/P-type), and insulating layers (SiO₂/AlN/Si₃N₄) per device requirements.
· Process Consultation: Recommend Smart Cut™ (high precision) or Grinding+CMP (cost-effective) solutions with comparative data.
· Wafer-Level Testing: Includes interface state analysis, thermal resistance mapping, and high-voltage reliability validation.
1. Q: What is SICOI wafer?
A: SICOI (Silicon Carbide on Insulator) wafer is an advanced composite substrate integrating single-crystal 4H-SiC film with SiO₂ insulating layer on silicon/sapphire base, enabling high-power and RF devices with superior thermal/electrical performance.
2. Q: How does SICOI compare to SOI?
A: SICOI offers 5x higher thermal conductivity (>300W/m·K) and 3x greater breakdown voltage (>8MV/cm) than SOI, making it ideal for 800V+ power electronics and 5G mmWave applications.
Tag: #4inch 6inch 8inch, #Customized, #4H-SiCOI Wafers, #Composite SiC on Insulator Substrates, #SiC, #SiO2, #Si